Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important. In addition, the alignment and arrangement of circuit features has become increasingly important as the size of such devices is mitigated.
A variety of approaches to the arrangement and manufacture of semiconductor devices involve the organization and alignment of a variety of circuit elements. One type of application wherein the alignment of adjacent circuits is important is semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F2 and 120 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor (e.g., a metal-oxide field-effect transistor (MOSFET)) to complicated quantum-effect devices. Conventional NDR-based SRAM cells, however, have problems that have prohibited their use in commercial SRAM products. These problems include, for example: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin-capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the thyristor gate and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design, including those employing thin capacitively-coupled thyristor-type devices, includes forming devices with aligned regions, and effecting the alignment using a method of manufacturing that is efficient and reliable.
In a variety of semiconductor devices, such as thin capacitively-coupled thyristor devices, junction leakage can also be a problem. In thin-capacitively-coupled thyristor-type NDR devices, junction leakage can occur when the thyristor gate capacitively couples a voltage pulse to a thyristor base region that is adjacent the base region directly underlying the thyristor gate. This junction leakage can adversely affect the performance, for example, the switching speed or stability of the thyristor-based circuit.
These and other design considerations have presented challenges to efforts to implement devices in a variety of applications, and in particular to devices in highly dense applications.